Hierarchy |
Input |
Constant Input |
Unused Input |
Floating Input |
Output |
Constant Output |
Unused Output |
Floating Output |
Bidir |
Constant Bidir |
Unused Bidir |
Input only Bidir |
Output only Bidir |
inst4 |
78 |
0 |
24 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst11 |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst3 |
2 |
0 |
0 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst5 |
78 |
0 |
24 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst10 |
8 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst1 |
36 |
3 |
1 |
3 |
15 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|irq_mapper |
3 |
31 |
2 |
31 |
32 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_011|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_011 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_010|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_010 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_009|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_009 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_008|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_008 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_007|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_007 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_006|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_006 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_005|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_005 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_004|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_004 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_003|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_003 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_002|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_002 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_001|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser_001 |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|crosser|clock_xer |
109 |
0 |
0 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|crosser |
111 |
4 |
0 |
4 |
107 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter_003|width_adapter_003|uncompressor |
33 |
4 |
0 |
4 |
24 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter_003|width_adapter_003 |
92 |
3 |
0 |
3 |
105 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter_003 |
92 |
3 |
0 |
3 |
105 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter_002|width_adapter_002 |
110 |
3 |
0 |
3 |
87 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter_002 |
110 |
3 |
0 |
3 |
87 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter_001|width_adapter_001|uncompressor |
33 |
4 |
0 |
4 |
24 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter_001|width_adapter_001 |
83 |
3 |
0 |
3 |
105 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter_001 |
83 |
3 |
0 |
3 |
105 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter|width_adapter |
110 |
3 |
0 |
3 |
78 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|width_adapter |
110 |
3 |
0 |
3 |
78 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_mux_001|arb|adder |
36 |
18 |
0 |
18 |
18 |
18 |
18 |
18 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_mux_001|arb |
13 |
0 |
4 |
0 |
9 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_mux_001 |
939 |
0 |
0 |
0 |
113 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_mux|arb|adder |
8 |
4 |
0 |
4 |
4 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_mux|arb |
6 |
0 |
4 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_mux |
211 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux_008 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux_007 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux_006 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux_005 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux_004 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux_003 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux_002 |
107 |
1 |
2 |
1 |
105 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux_001 |
108 |
4 |
2 |
4 |
209 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|rsp_xbar_demux |
108 |
4 |
2 |
4 |
209 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|cmd_xbar_mux_001|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst|cmd_xbar_mux_001|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cmd_xbar_mux_001 |
211 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cmd_xbar_mux|arb|adder |
8 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst|cmd_xbar_mux|arb |
6 |
0 |
1 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cmd_xbar_mux |
211 |
0 |
0 |
0 |
106 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cmd_xbar_demux_001 |
115 |
81 |
2 |
81 |
937 |
81 |
81 |
81 |
0 |
0 |
0 |
0 |
0 |
inst|cmd_xbar_demux |
108 |
4 |
2 |
4 |
209 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_004|rst_controller_004|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_004|rst_controller_004 |
17 |
16 |
0 |
16 |
2 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_004 |
17 |
16 |
0 |
16 |
2 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_003|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_003|rst_controller_001 |
17 |
15 |
0 |
15 |
2 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_003 |
17 |
15 |
0 |
15 |
2 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_002|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_002|rst_controller_001 |
17 |
15 |
0 |
15 |
2 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_002 |
17 |
15 |
0 |
15 |
2 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_001|rst_controller_001|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_001|rst_controller_001 |
17 |
15 |
0 |
15 |
2 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller_001 |
17 |
15 |
0 |
15 |
2 |
15 |
15 |
15 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller|rst_controller|alt_rst_sync_uq1 |
2 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller|rst_controller |
17 |
14 |
0 |
14 |
2 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
inst|rst_controller |
17 |
14 |
0 |
14 |
2 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
inst|burst_adapter_001|burst_adapter_001|altera_merlin_burst_adapter_uncompressed_only.the_ba |
89 |
3 |
5 |
3 |
87 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|burst_adapter_001|burst_adapter_001 |
89 |
0 |
0 |
0 |
87 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|burst_adapter_001 |
89 |
0 |
0 |
0 |
87 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|burst_adapter|burst_adapter|altera_merlin_burst_adapter_uncompressed_only.the_ba |
80 |
3 |
5 |
3 |
78 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|burst_adapter|burst_adapter |
80 |
0 |
0 |
0 |
78 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|burst_adapter |
80 |
0 |
0 |
0 |
78 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_008|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_008 |
80 |
0 |
2 |
0 |
87 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_007|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_007 |
98 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_006|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_006 |
98 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_005|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_005 |
98 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_004|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_004 |
71 |
0 |
2 |
0 |
78 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_003|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_003 |
98 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_002|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_002 |
98 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_001|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router_001 |
98 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|id_router|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|id_router |
98 |
0 |
2 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|addr_router_001|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|addr_router_001 |
98 |
0 |
6 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|addr_router|the_default_decode |
0 |
13 |
0 |
13 |
13 |
13 |
13 |
13 |
0 |
0 |
0 |
0 |
0 |
inst|addr_router |
98 |
0 |
6 |
0 |
105 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator_avalon_universal_slave_0_agent_rdata_fifo|adc_s0_translator_avalon_universal_slave_0_agent_rdata_fifo |
63 |
80 |
0 |
80 |
59 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator_avalon_universal_slave_0_agent_rdata_fifo |
63 |
80 |
0 |
80 |
59 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|adc_s0_translator_avalon_universal_slave_0_agent_rsp_fifo |
120 |
76 |
0 |
76 |
116 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator_avalon_universal_slave_0_agent_rsp_fifo |
120 |
76 |
0 |
76 |
116 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator_avalon_universal_slave_0_agent|adc_s0_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator_avalon_universal_slave_0_agent|adc_s0_translator_avalon_universal_slave_0_agent |
209 |
23 |
30 |
23 |
219 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator_avalon_universal_slave_0_agent |
209 |
4 |
0 |
4 |
219 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator_avalon_universal_slave_0_agent_rdata_fifo|pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo |
79 |
80 |
0 |
80 |
75 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator_avalon_universal_slave_0_agent_rdata_fifo |
79 |
80 |
0 |
80 |
75 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent |
277 |
40 |
46 |
40 |
290 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator_avalon_universal_slave_0_agent |
277 |
4 |
0 |
4 |
290 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo|pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo |
79 |
80 |
0 |
80 |
75 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rdata_fifo |
79 |
80 |
0 |
80 |
75 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent |
277 |
40 |
46 |
40 |
290 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator_avalon_universal_slave_0_agent |
277 |
4 |
0 |
4 |
290 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo |
79 |
80 |
0 |
80 |
75 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator_avalon_universal_slave_0_agent_rdata_fifo |
79 |
80 |
0 |
80 |
75 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent |
277 |
40 |
46 |
40 |
290 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator_avalon_universal_slave_0_agent |
277 |
4 |
0 |
4 |
290 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator_avalon_universal_slave_0_agent_rdata_fifo|lcd_s0_translator_avalon_universal_slave_0_agent_rdata_fifo |
55 |
80 |
0 |
80 |
51 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator_avalon_universal_slave_0_agent_rdata_fifo |
55 |
80 |
0 |
80 |
51 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator_avalon_universal_slave_0_agent_rsp_fifo|lcd_s0_translator_avalon_universal_slave_0_agent_rsp_fifo |
111 |
76 |
0 |
76 |
107 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator_avalon_universal_slave_0_agent_rsp_fifo |
111 |
76 |
0 |
76 |
107 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator_avalon_universal_slave_0_agent|lcd_s0_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator_avalon_universal_slave_0_agent|lcd_s0_translator_avalon_universal_slave_0_agent |
175 |
14 |
22 |
14 |
183 |
14 |
14 |
14 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator_avalon_universal_slave_0_agent |
175 |
4 |
0 |
4 |
183 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo|pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo |
79 |
80 |
0 |
80 |
75 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator_avalon_universal_slave_0_agent_rdata_fifo |
79 |
80 |
0 |
80 |
75 |
80 |
80 |
80 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent |
277 |
40 |
46 |
40 |
290 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator_avalon_universal_slave_0_agent |
277 |
4 |
0 |
4 |
290 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent |
277 |
40 |
46 |
40 |
290 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart_avalon_jtag_slave_translator_avalon_universal_slave_0_agent |
277 |
4 |
0 |
4 |
290 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2_s1_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2_s1_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2_s1_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent |
277 |
40 |
46 |
40 |
290 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2_s1_translator_avalon_universal_slave_0_agent |
277 |
4 |
0 |
4 |
290 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent_rsp_fifo |
138 |
76 |
0 |
76 |
134 |
76 |
76 |
76 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|uncompressor |
33 |
1 |
0 |
1 |
31 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent |
277 |
40 |
46 |
40 |
290 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_jtag_debug_module_translator_avalon_universal_slave_0_agent |
277 |
4 |
0 |
4 |
290 |
4 |
4 |
4 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_data_master_translator_avalon_universal_master_0_agent |
168 |
40 |
72 |
40 |
133 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_instruction_master_translator_avalon_universal_master_0_agent |
168 |
40 |
72 |
40 |
133 |
40 |
40 |
40 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator|adc_s0_translator |
66 |
21 |
8 |
21 |
61 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
inst|adc_s0_translator |
66 |
21 |
0 |
21 |
61 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator|pwm_s0_translator |
101 |
23 |
8 |
23 |
97 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
inst|pwm_s0_translator |
101 |
23 |
0 |
23 |
97 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator|altpll_0_pll_slave_translator |
101 |
27 |
15 |
27 |
90 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0_pll_slave_translator |
101 |
27 |
0 |
27 |
90 |
27 |
27 |
27 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator|pio_jsb_s1_translator |
101 |
55 |
18 |
55 |
84 |
55 |
55 |
55 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb_s1_translator |
101 |
55 |
0 |
55 |
84 |
55 |
55 |
55 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator|lcd_s0_translator |
48 |
21 |
8 |
21 |
43 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
inst|lcd_s0_translator |
48 |
21 |
0 |
21 |
43 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator|pio_led_s1_translator |
101 |
21 |
18 |
21 |
84 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led_s1_translator |
101 |
21 |
0 |
21 |
84 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart_avalon_jtag_slave_translator|jtag_uart_avalon_jtag_slave_translator |
101 |
19 |
19 |
19 |
83 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart_avalon_jtag_slave_translator |
101 |
19 |
0 |
19 |
83 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2_s1_translator|onchip_memory2_s1_translator |
101 |
23 |
4 |
23 |
101 |
23 |
23 |
23 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2_s1_translator |
101 |
22 |
0 |
22 |
101 |
22 |
22 |
22 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_jtag_debug_module_translator|cpu_jtag_debug_module_translator |
101 |
21 |
8 |
21 |
97 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_jtag_debug_module_translator |
101 |
21 |
0 |
21 |
97 |
21 |
21 |
21 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_data_master_translator|cpu_data_master_translator |
102 |
19 |
0 |
19 |
99 |
19 |
19 |
19 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_data_master_translator |
102 |
16 |
0 |
16 |
99 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_instruction_master_translator|cpu_instruction_master_translator |
102 |
58 |
0 |
58 |
99 |
58 |
58 |
58 |
0 |
0 |
0 |
0 |
0 |
inst|cpu_instruction_master_translator |
102 |
54 |
0 |
54 |
99 |
54 |
54 |
54 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_15 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_14 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_13 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_12 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_11 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_10 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_9 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_8 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_7 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_6 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_5 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_4 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_3 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_2 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_1 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc|register_0 |
21 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|adc|adc |
287 |
467 |
0 |
467 |
291 |
467 |
467 |
467 |
0 |
0 |
0 |
0 |
0 |
inst|adc |
287 |
467 |
0 |
467 |
291 |
467 |
467 |
467 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_15 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_14 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_13 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_12 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_11 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_10 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_9 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_8 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_7 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_6 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_5 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_4 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_3 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_2 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_1 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm|register_0 |
39 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|pwm|pwm |
561 |
897 |
0 |
897 |
567 |
897 |
897 |
897 |
0 |
0 |
0 |
0 |
0 |
inst|pwm |
561 |
897 |
0 |
897 |
567 |
897 |
897 |
897 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0|sd1 |
3 |
1 |
0 |
1 |
6 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0|stdsync2|dffpipe3 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0|stdsync2 |
3 |
0 |
0 |
0 |
1 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|altpll_0 |
39 |
31 |
30 |
31 |
38 |
31 |
31 |
31 |
0 |
0 |
0 |
0 |
0 |
inst|pio_jsb |
12 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2|the_altsyncram|auto_generated |
52 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|onchip_memory2 |
55 |
0 |
1 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_15 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_14 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_13 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_12 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_11 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_10 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_9 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_8 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_7 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_6 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_5 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_4 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_3 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_2 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_1 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd|register_0 |
12 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|lcd|lcd |
149 |
233 |
0 |
233 |
155 |
233 |
233 |
233 |
0 |
0 |
0 |
0 |
0 |
inst|lcd |
149 |
233 |
0 |
233 |
155 |
233 |
233 |
233 |
0 |
0 |
0 |
0 |
0 |
inst|pio_led |
38 |
24 |
24 |
24 |
40 |
24 |
24 |
24 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r|rfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r|rfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_r |
13 |
0 |
1 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|wr_ptr |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|rd_ptr_count |
4 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram|altsyncram1 |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|FIFOram |
24 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state|count_usedw |
5 |
0 |
0 |
0 |
6 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo|fifo_state |
5 |
0 |
0 |
0 |
8 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w|wfifo|auto_generated|dpfifo |
13 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w|wfifo|auto_generated |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart|the_zebra_nios_sopc_jtag_uart_scfifo_w |
12 |
0 |
0 |
0 |
16 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|jtag_uart |
38 |
10 |
23 |
10 |
34 |
10 |
10 |
10 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_jtag_debug_module_wrapper|the_zebra_nios_sopc_cpu_jtag_debug_module_sysclk |
43 |
0 |
0 |
0 |
51 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_jtag_debug_module_wrapper|the_zebra_nios_sopc_cpu_jtag_debug_module_tck |
130 |
0 |
1 |
0 |
43 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_jtag_debug_module_wrapper |
123 |
0 |
0 |
0 |
53 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_im |
97 |
36 |
93 |
36 |
48 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_pib |
39 |
20 |
38 |
20 |
19 |
20 |
20 |
20 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_fifo|the_zebra_nios_sopc_cpu_oci_test_bench |
36 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_fifo|zebra_nios_sopc_cpu_nios2_oci_fifocount_inc_fifocount |
5 |
0 |
0 |
0 |
5 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_fifo|zebra_nios_sopc_cpu_nios2_oci_fifowp_inc_fifowp |
4 |
2 |
0 |
2 |
4 |
2 |
2 |
2 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_fifo|zebra_nios_sopc_cpu_nios2_oci_compute_tm_count_tm_count |
3 |
0 |
0 |
0 |
2 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_fifo |
151 |
0 |
65 |
0 |
36 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_dtrace|zebra_nios_sopc_cpu_nios2_oci_trc_ctrl_td_mode |
9 |
0 |
6 |
0 |
4 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_dtrace |
102 |
0 |
91 |
0 |
72 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_itrace |
25 |
17 |
23 |
17 |
87 |
17 |
17 |
17 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_dbrk |
87 |
0 |
0 |
0 |
91 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_xbrk |
53 |
5 |
50 |
5 |
6 |
5 |
5 |
5 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_break |
52 |
36 |
6 |
36 |
71 |
36 |
36 |
36 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_avalon_reg |
48 |
0 |
29 |
0 |
68 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_ocimem|zebra_nios_sopc_cpu_ociram_sp_ram|the_altsyncram|auto_generated |
46 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_ocimem|zebra_nios_sopc_cpu_ociram_sp_ram |
46 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_ocimem |
91 |
0 |
6 |
0 |
65 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci|the_zebra_nios_sopc_cpu_nios2_oci_debug |
50 |
1 |
30 |
1 |
7 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_nios2_oci |
155 |
0 |
0 |
0 |
69 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|zebra_nios_sopc_cpu_register_bank_b|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|zebra_nios_sopc_cpu_register_bank_b |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|zebra_nios_sopc_cpu_register_bank_a|the_altsyncram|auto_generated |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|zebra_nios_sopc_cpu_register_bank_a |
44 |
0 |
0 |
0 |
32 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
inst|cpu|the_zebra_nios_sopc_cpu_test_bench |
269 |
3 |
232 |
3 |
34 |
3 |
3 |
3 |
0 |
0 |
0 |
0 |
0 |
inst|cpu |
148 |
1 |
31 |
1 |
109 |
1 |
1 |
1 |
0 |
0 |
0 |
0 |
0 |
inst |
82 |
8 |
0 |
8 |
199 |
8 |
8 |
8 |
0 |
0 |
0 |
0 |
0 |
inst6 |
2 |
16 |
0 |
16 |
67 |
16 |
16 |
16 |
0 |
0 |
0 |
0 |
0 |